A PLD (Programmable Logic Device) such as an FPGA (Field-Programmable Gate Array), which is capable of switching a circuit configuration, is widely used. The applicant or the inventor has been developing an “MPLD (Memory-based Programmable Logic Device)” (Registered trademark), which can realize circuit configuration by a memory cell unit. An MPLD is described, for example, in the following Patent Literature 1. The MPLD connects memory arrays each of which is referred to as an MLUT (Multi Look-Up-Table) with each other. The MLUT stores truth value data and configures the wiring element and the logic element. The MPLD places such MLUTs in arrays and connects the same with each other, whereby realizes the function approximately the same as that of the FPGA.
Further, the MPLD is a device which offers flexibility to the logic area and the wiring area by using the MLUTs as both the logic element and the wiring element. Such feature is different from an FPGA which has a dedicated switch circuit for connecting the memory units with each other.
The optimal arrangement and wiring methods for the FPGA are already considered (Patent Literature 2). In the case of arranging and wiring MPLD, the MLUTs operate as the logic element and/or the connection element, whereby the writing in of the truth value table data to the MLUTs means arrangement of the logic operation and/or the wiring between the MLUTs. Accordingly, the creation of the truth value table data for the writing in to MLUTs corresponds to “arrangement and wiring” of MPLD, although the optimal arrangement and wiring method for the MPLD has not been disclosed.